Title:
半導体ウェハフィーチャを製作するための方法
Document Type and Number:
Japanese Patent JP7232901
Kind Code:
B2
Abstract:
A system and method are provided for fabricating semiconductor wafer features with controlled dimensions. In use, a top surface of a semiconductor wafer is identified. A first portion of the top surface of the semiconductor wafer is then vertically etched to form a step down from a second portion of the top surface of the semiconductor wafer, the step comprised of a horizontal face and a vertical sidewall. Additionally, a film is uniformly deposited across the horizontal face and the vertical sidewall of the step. Further, the second portion of the top surface of the semiconductor wafer is vertically etched to expose, as a feature of the semiconductor wafer, the film deposited across the vertical sidewall of the step.
Inventors:
Cree Falhart
Application Number:
JP2021512670A
Publication Date:
March 03, 2023
Filing Date:
September 05, 2019
Export Citation:
Assignee:
KLA Corporation
International Classes:
H01L21/66
Domestic Patent References:
| JP2016154234A | ||||
| JP2008513973A | ||||
| JP2006237620A | ||||
| JP2017191938A | ||||
| JP2018085504A | ||||
| JP2008134103A |
Foreign References:
| US20070082437 | ||||
| US20060281266 | ||||
| US20140346612 | ||||
| US20120181665 |
Attorney, Agent or Firm:
Patent Attorney Corporation YKI International Patent Office