Title:
METHOD OF FORMING LAYOUT OF TRANSISTORS AND DEVICE OF FORMING LAYOUT OF TRANSISTORS
Document Type and Number:
Japanese Patent JP3175532
Kind Code:
B2
Abstract:
PURPOSE: To realize a high density cell design, that is similar to the cell design manually done in many hours, in a short time by repeating each step of mutual connection data of transistors, in which optimizing the combination and the layout of the transistors for achieving common diffusion.
CONSTITUTION: P-type transistors 1 and N-type transistors 2 are arranged so that each group makes a row to form two rows (a) and channel wiring 3 is used for interconnection of the two rows of transistors. The direction of the rows can be freely determined other than the horizontal one. It comprises the step of the grouping of transistors for attaining the common diffusion, the step of correcting the status of the common diffusion and the step of optimizing the layout of the groups. Selecting the necessary steps, the optimization of the combination and the layout of the common diffusion for the transistors are performed by repeating it. Therefore, the high density layout of the cells is composed by the flexible processing of layout wiring similar to the one by the manual designing.
Inventors:
Masahiro Fukui
Application Number:
JP11817695A
Publication Date:
June 11, 2001
Filing Date:
May 17, 1995
Export Citation:
Assignee:
Matsushita Electric Industrial Co., Ltd
International Classes:
H01L21/82; G06F17/50; (IPC1-7): H01L21/82; G06F17/50
Domestic Patent References:
| JP794591A |
Other References:
【文献】福井正博,秋濃俊郎、“VLSIのリーフセル合成に関する一手法(コンパクション方法の開発とその評価”、電子情報通信学会技術研究報告[VLSI設計技術]、1994年、VOL.94、No.315、13~17頁
Attorney, Agent or Firm:
Fumio Iwahashi (2 others)
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