Title:
METHOD OF FORMING MIS SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP3866167
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a method of easily forming a gate-overlapped LDD structure (GOLD) in which even the LDD is overlapped with a gate electrode.
SOLUTION: A central part 104 of the gate electrode is formed on an insulating film 103, which is formed on a semiconductor substrate 101, and low concentration regions 105/106 are formed with a self-aligned manner. An electrically conductive coating film 107 is formed on the insulating film and on the central part of the gate electrode. The surface of the electrically conductive coating film is plasma-treated in an atmosphere containing argon, and the electrically conductive coating film is anisotropically etched in an atmosphere containing halogen fluoride. Gate-electrode side members 109 are formed on the sides of the central part of the gate electrode. Thereafter, a source and a drain are formed by ion implantation.
Inventors:
Hideomi Suzawa
Shunpei Yamazaki
Yasuhiko Takemura
Shunpei Yamazaki
Yasuhiko Takemura
Application Number:
JP2002210564A
Publication Date:
January 10, 2007
Filing Date:
November 25, 1994
Export Citation:
Assignee:
Semiconductor Energy Laboratory Co., Ltd.
International Classes:
H01L21/28; H01L29/78; H01L21/3065; H01L21/336; H01L29/423; H01L29/49; (IPC1-7): H01L29/78; H01L21/28; H01L21/3065; H01L21/336; H01L29/423; H01L29/49
Domestic Patent References:
| JP57500399A | ||||
| JP4260333A | ||||
| JP4334022A | ||||
| JP5136096A |