Title:
METHOD FOR FORMING WIRING
Document Type and Number:
Japanese Patent JP3913196
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To prevent the interwiring short of a damascene structure.
SOLUTION: An insulating film 2 formed on a substrate 1 is formed with a proximity wiring groove 3, and a barrier film 4 and a conductive film 5 are deposited. The conductive film 5 and the barrier film 4 as portions projected from the wiring groove 3 are removed by a CMP process. In this case, the surface of the insulating film 2 between the wiring grooves 3 is scratched in the CMP process, and a portion of the conductive film 5(conductive film materials 6) are embedded in the scratch, and a short status may be generated between wiring. Then, any foreign matter such as polish waste 7 remaining on the surface of the substrate is removed, oxidant 8 is supplied to the surface of the substrate, and the conductive materials 6 embedded in the scratch on the surface of the insulating film 2 are oxidized. Then, oxide 6a is removed in the CMP process so that the generation of inter-wiring short can be prevented.
Inventors:
Kenji Kobayashi
Application Number:
JP2003162217A
Publication Date:
May 09, 2007
Filing Date:
June 06, 2003
Export Citation:
Assignee:
Matsushita Electric Industrial Co., Ltd
International Classes:
H01L21/3205; H01L21/304; (IPC1-7): H01L21/3205; H01L21/304
Domestic Patent References:
| JP7233485A | ||||
| JP8153698A | ||||
| JP2000315666A | ||||
| JP2002083787A | ||||
| JP11330023A | ||||
| JP2001156029A | ||||
| JP9167797A | ||||
| JP8083780A |
Attorney, Agent or Firm:
Akio Miyai
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