To provide hardware information which is appropriate for implementing a loop processing in a device which can reconfigure a circuit and has a plurality of processing elements.

In a compiler 60, hardware information 62 including a 1st configuration information 63a, a 2nd configuration information 63b, a 3rd configuration information 63c, a 4th configuration information 63d, and a 5th configuration information 63e for a source program 61 are generated. The 1st configuration information 63a is used to configure a data pass which executes a 1st processing repeatedly performed with a 1st algorithm. The 2nd configuration information 63b is used to execute loading input data from a 1st memory by a first address counter. The 3rd configuration information 63c is used to execute storing output data in a second memory by a second address counter. The 4th configuration information 63d is used to execute loading the input data in the 1st memory from an external memory by a 3rd address counter. The 5th configuration information 63e is used to execute the output data in the external memory from the 2nd memory by a 4th address counter.