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Title:
METHOD FOR INSPECTING INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JPH04177848
Kind Code:
A
Abstract:

PURPOSE: To prevent marking on a nondefective chip and eliminate unnecessary preliminary test by marking on a chip judged defective after a preset number of acceptable chip is reached.

CONSTITUTION: A wafer to be measured is placed on a stage and the probe of a probing device is set on the wafer. The input of a marking device is turned off and the number to be measured is set. Then, nondefective number is set and the measurement is started. The chip measurement is continued until it reaches the number to be measured, and when the nondefective number reaches the set number, the marking device is turned on and the measurement of the remaining chips of the wafer is started. When the measured chip is nondefective, the chip is left without a mark, and when it is defective, the chip is marked. Thus, the nondefective chip is prevented from being marked by the mismatch of the measuring condition and preliminary test is eliminated.


Inventors:
SUETSUGU TOSHIYUKI
Application Number:
JP30689990A
Publication Date:
June 25, 1992
Filing Date:
November 13, 1990
Export Citation:
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Assignee:
KYUSHU NIPPON ELECTRIC
International Classes:
H01L21/66; (IPC1-7): H01L21/66
Attorney, Agent or Firm:
Uchihara Shin



 
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