To improve efficiency in laying out and wiring a reconfigurable semiconductor device.

A semiconductor device comprises a plurality of memory cell units that constitute an array and are connected with each other. The memory cell units operate as logical elements when a truth table data, which is constituted so as to output a logical operation of an input value specified by a plurality of addresses to a data line, is written; and operates as connection elements when a truth table data, which is constituted so as to output an input value specified by an address to a data line connected to the address of another memory cell unit, is written. To lay out and wire the semiconductor device, a net list is generated on the basis of a circuit description of circuit configuration; a sequential circuit set to be scanned is extracted from the net list; a first truth table set to be written to a first set of the memory cell units is generated from the sequential circuit set to be scanned; and a second truth table set to be written to a second set of the memory cell units is generated from a combinational logical circuit set of the net list.