To provide a method for manufacturing an NAND flash memory element for adjusting the leakage currents of a select transistor.

This method for manufacturing an NAND flash memory element equipped with a memory cell and a select transistor is provided to present a graph where the leakage currents of a select transistor are shown for every gate electrode length of the select transistor, and to present a graph where the leakage currents of the select transistor are shown by every memory cell threshold voltage ion injection doze quantity. This method comprises a step for searching the leakage currents of the select transistor pertinent to the gate length of the current select transistor, and for searching the memory cell threshold voltage ion injection doze quantity pertinent to the leakage currents and a step for searching the leakage currents of the select transistor so that the memory cell threshold voltage ion injection doze amounts can be made equal to requested memory cell threshold voltage ion injection doze quantity, and for searching and increasing the gate length of the select transistor pertinent to the leakage currents of the select transistor.