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Title:
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP2010016398
Kind Code:
A
Abstract:

To provide a means for improving the adhesion of a semiconductor configuration to an insulating layer and to an upperlayer insulating film, in a semiconductor device having: the semiconductor configuration, called CSP (chip size package), provided on a base plate; the insulating layer provided on the base plate in a periphery of the semiconductor configuration; and the upperlayer insulating film and an upperlayer wiring, both provided on the semiconductor configuration and the insulating layer.

The semiconductor configuration 2 is provided on an upper surface of the base plate 1 through an adhesion layer 3. Adhesion-improving films 14a, 14b and 14c are provided on a side surface or an upper surface of the semiconductor configuration 2 and on the upper surface of the base plate 1, wherein the adhesion-improving films includes a silane coupling agent. The insulating layer 15 is provided on an upper surface of the adhesion-improving film 14b in the periphery of the adhesion-improving film 14a. The upperlayer insulating layer 16 is provided on an upper surface of the adhesion-improving film 14c and insulating film 15. Also, the adhesion-improving film comprising the silane coupling agent may be provided between the semiconductor configuration 2 and the adhesion layer 3 and between the base plate 1 and the adhesion layer 3.


Inventors:
OKADA OSAMU
SADABETTO HIROYASU
Application Number:
JP2009210588A
Publication Date:
January 21, 2010
Filing Date:
September 11, 2009
Export Citation:
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Assignee:
CASIO COMPUTER CO LTD
NIPPON CMK KK
International Classes:
H01L23/12; H01L21/56
Domestic Patent References:
JP2003298005A2003-10-17
JP2004095836A2004-03-25
JP2003332482A2003-11-21
JP2003249691A2003-09-05
JPH08264686A1996-10-11
JP2001244383A2001-09-07
Attorney, Agent or Firm:
Hidemi Kashima