METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT AND SEMICONDUCTOR DEVICE

Title:

METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT AND SEMICONDUCTOR DEVICE

Document Type and Number:

Japanese Patent JP2003124276

Kind Code:

A

Abstract:

To solve the problem that the number of mounted chip regions obtained from one semiconductor wafer is limited and it becomes an obstacle for reducing the cost of LSI since an inspection circuit region and the mounted chip region being the object for inspection are arranged on a semiconductor wafer in a pair in a conventional case.

Chip region selection circuits 209 and 210 and a chip region selection signal input terminal 208 are disposed in the inspection circuit region 206 on the semiconductor wafer. Thus, one inspection circuit region 206 can be shared by the two mounted chip regions 201 and 202. Consequently, the number of the inspection circuit regions arranged on one semiconductor wafer can remarkably be reduced, and therefore the number of the mounted chip regions obtained from one semiconductor wafer can be increased.

Inventors:

NAKAMURA TOSHIHIRO
OTA KIYOTO
SUZUKI RIICHI

Application Number:

JP2001320140A

Publication Date:

April 25, 2003

Filing Date:

October 18, 2001

Export Citation:

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Assignee:

MATSUSHITA ELECTRIC IND CO LTD

International Classes:

G01R31/28; H01L21/66; H01L21/822; H01L27/04; (IPC1-7): H01L21/66; G01R31/28; H01L21/822; H01L27/04

Attorney, Agent or Firm:

Miyai Akio

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