Title:
METHOD FOR MANUFACTURING WIRING BOARD
Document Type and Number:
Japanese Patent JP2015088628
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To provide a wiring board which allows a semiconductor device to operate with stability.SOLUTION: A method for manufacturing a wiring board A comprises: the first step of forming a plurality of wiring line conductors 2 electrically independent of each other and each having a plating region M1 and a non-plating region N1; the second step of depositing an electrically-connecting layer 7 for electrically connecting the wiring line conductors 2 to each other; the third step of forming an etching resist R1 so as to expose the plating regions M1 and parts of the electrically-connecting layer 7 around them and cover remaining parts; the fourth step of exposing the plating regions M1 with the wiring line conductors 2 connected by the electrically-connecting layer 7; the fifth step of forming a plating resist R2 to cover the non-plating regions N1 while exposing the plating regions M1; and the sixth step of depositing an electrolytic plating layer 4 on the plating regions M1. In the third step, a wiring line conductor part 2a of each wiring line conductor, which is covered with the etching resist R1, is 50 μm or less in length. In the fifth step, parts of the electrically-connecting layer 7 adjacent to the plating regions M1 are exposed from the plating resist R2. In the sixth step, the electrolytic plating layer 4 is deposited over a range from each exposed part of the electrically-connecting layer 7 to the plating region M1.
Inventors:
ARAKAWA YOSUKE
Application Number:
JP2013226099A
Publication Date:
May 07, 2015
Filing Date:
October 31, 2013
Export Citation:
Assignee:
KYOCERA CIRCUIT SOLUTIONS INC
International Classes:
H05K3/18; H01L23/12; H05K3/34
Domestic Patent References:
| JP2007324568A | 2007-12-13 | |||
| JP2003013281A | 2003-01-15 | |||
| JP2007095743A | 2007-04-12 |
Foreign References:
| US6576540B2 | 2003-06-10 |