To reduce a simulation load, shorten a turnaround time for a desired fault detection rate to be reached, and calculate a fault detection rate without an error by a degeneration fault.

A test object logic circuit 2 comprises a plurality of combined circuit blocks and flip-flops connecting them. A simulation part 4, with a single simulation, collects values of the flip-flops for holding input values to each combined circuit block, as flip-flop data 6. A fault detection rate calculation part 7 computes data indicating fault detectability in each combined circuit block with the input values input and determines external detectability of fault points included in the fault detectability data to calculate a fault detection rate 5 of a test pattern 3 for the test object logic circuit 2.