PURPOSE: To obtain accurate rising and falling delay times by measuring the H and L periods of the propagation signal of a measuring circuit to which a circuit composed of a logic gate to be measured and a gate circuit is connected.

CONSTITUTION: An even number of two-input NAND gates 11-1-11-n which have equal characteristics are provided as logic gates to be measured, and an odd number of inverters 12-0 and 12-n which have equal characteristics as gate circuits are provided with CMOS inverters which have equal rising and falling delay times. Then (n) stages of unit circuits 10-1 to 10-n wherein the gates 11-1 to 11-n and inverters 12-1 and 12-n are connected in series are cascaded to constitute the measuring circuit. This circuit is oscillated for measurement and the H-level and L-level periods of the signal of the output H of the inverter 12-0 which is inverted and propagated successively are measured; and the delay times of the gate circuits are subtracted from them and the results are divided by (n) respectively to calculate the rising and falling delay times of one logic gate to be measured.