Title:
METHOD FOR OUTPUTTING FRAME SYNCHRONIZING SIGNAL AND CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JP3811222
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To detect the position of '0' code capable of satisfying a highly accurate request and to reduce cost by mutually comparing specific long-turm and short-term output signals.
SOLUTION: An average part 8 forms a short-term output signal P0 by averaging instantaneous output values corresponding to the prescribed number D0 of sampling values. The code P0 due to the same information contents is applied to an output signal from a decimation circuit 9 and the output signal is supplied to a digital filter 10 and a long-term output detecting circuit 11. The circuit 11 finds out the long-term output of the signal P0 for an extremely long period, e.g. D1=512 sampling values. A subtractor 12 forms a differential signal P by finding out a difference between output signals P2, P1 from the filter 10 and the circuit 11 and supplies the signal P to a threshold circuit 13 and a threshold TH corresponds to a long-term output signal outputted from the output side of the circuit 11 and weighted by a coefficient αT. When the signal P exceeds the threshold TH, the signal P is supplied to a maximum value detector 15, so that the '0' code can be accurately positioned.
Inventors:
Michael Bole
Marx Steppen
Marx Steppen
Application Number:
JP15987496A
Publication Date:
August 16, 2006
Filing Date:
June 20, 1996
Export Citation:
Assignee:
ROBERT BOSCH GMBH
International Classes:
H04L7/08; H04L27/22; H04J1/00; H04J11/00; H04L27/26; (IPC1-7): H04L7/08; H04J1/00; H04L27/22
Domestic Patent References:
| JP3297239A |
Attorney, Agent or Firm:
Toshio Yano
Toshiomi Yamazaki
Reinhard Einsel
Toshiomi Yamazaki
Reinhard Einsel