METHOD AND PROGRAM OF VERIFYING SEMICONDUCTOR DEVICE PATTERN

Title:

METHOD AND PROGRAM OF VERIFYING SEMICONDUCTOR DEVICE PATTERN

Document Type and Number:

Japanese Patent JP2011141491

Kind Code:

A

Abstract:

To provide a method and program of verifying a semiconductor device pattern, with which computational loads can be reduced and computational time can be reduced.

The method of verifying a semiconductor device pattern includes: a first step (ST11) to calculate a mask pattern; a second step (ST12) to calculate the shape of a photoresist formed on a semiconductor substrate; a third step (ST13) to perform uniform resizing using graphic processing and calculate only artificial temporary processing forms; a fourth step (ST14) to graphically verify whether a designing pattern is formed on the semiconductor substrate or not and to detect potentially risky places; and a fifth step (ST15) to simulate processing of the potentially risky places and calculate partial processing forms.

Inventors:

NAKAYAMA KOICHI
KOTANI TOSHIYA
KODAMA CHIKAAKI
NAKAJIMA FUMIHARU
MASHITA HIROMITSU
TAGUCHI TAKAFUMI

Application Number:

JP2010003308A

Publication Date:

July 21, 2011

Filing Date:

January 08, 2010

Export Citation:

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Assignee:

TOSHIBA CORP

International Classes:

G03F1/36; G03F1/68; G03F1/70; G06F17/50; H01L21/027; H01L21/82

Attorney, Agent or Firm:

Kurata Masatoshi
Satoshi Kono
Makoto Nakamura
Yoshihiro Fukuhara
Takashi Mine
Toshio Shirane
Sadao Muramatsu
Nobuhisa Nogawa
Kocho Chojiro
Naoki Kono
Katsu Sunagawa
Katsumura Hiro
Tatsushi Sato
Takashi Okada
Mihoko Horiuchi
Takenori Masanori
Takuzo Ichihara
Yamashita Gen

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