Title:
半導体デバイス及びメモリデバイスからデータを読み出すための方法
Document Type and Number:
Japanese Patent JP6496936
Kind Code:
B2
Abstract:
A method and system for suppressing power signature in a memory device during read operations. A memory array stores data in an even number of cells per bit, such as 2 cells per bit, where complementary data states are stored in each pair of cells. Differential read out of the memory array via the bitlines suppresses power signature because the same power consumption occurs regardless of the data being accessed from the memory array. Data output buffers that provide complementary data to a downstream circuit system are reset to the same logic state prior to every read operation such that only one output buffer (in the complementary output buffer pair) is ever driven to the opposite logic state in each read cycle. Hence the power consumption remains the same regardless of the data states being read out from the memory array and provided by the output buffers.
Inventors:
Urodek Kerjanowix
Betina hold
Betina hold
Application Number:
JP2016180703A
Publication Date:
April 10, 2019
Filing Date:
September 15, 2016
Export Citation:
Assignee:
SYN0PSYS, INC.
International Classes:
G06F21/79; G06F21/55; G11C11/419; H03K19/00
Domestic Patent References:
| JP64035679A | ||||
| JP2000515669A |
Foreign References:
| US20080205169 | ||||
| WO1998053459A1 | ||||
| US7719896 | ||||
| US8213211 |
Attorney, Agent or Firm:
Ikeda adult
Junichiro Sakamaki
Masakazu Noda
Kazuhiro Yamaguchi
Junichiro Sakamaki
Masakazu Noda
Kazuhiro Yamaguchi