Title:
キャパシタのノンリニアリティを補償するための方法および回路
Document Type and Number:
Japanese Patent JP3564066
Kind Code:
B2
Abstract:
Capacitor voltage coefficient errors are reduced in a lossy integrator by providing oppositely oriented first and second feedback capacitors in a switched capacitor feedback circuit coupled between the output and a summing conductor connected to an inverting input of an operational amplifier. During a first clock signal, terminals of the first feedback capacitor are coupled to a reference voltage by closing first and second reset switches and the second feedback capacitor is coupled between the inverting input and the output conductor by closing first and second sampling switches. Then, during a second clock signal the terminals of the second feedback capacitor are coupled to the first reference voltage by closing third and fourth reset switches, and the second feedback capacitor is coupled between the inverting input and the output by closing third and fourth sampling switches. The opposed orientations of the first and second feedback capacitors result in time-averaging of opposite polarity voltage coefficient error charge contributions into the inverting input by the first and second feedback capacitors. In one embodiment, data-dependent flow of charge into a "quiet" reference voltage source is avoided by first coupling a capacitor to an auxiliary reference voltage source that is substantially equal to the quiet reference voltage, and later coupling the capacitor to the quiet reference voltage source.
Inventors:
Forwards, paul
Application Number:
JP2000547575A
Publication Date:
September 08, 2004
Filing Date:
May 06, 1999
Export Citation:
Assignee:
BURR-BROWN CORPORATION
International Classes:
H03M1/66; G06G7/186; G11C27/02; H03M3/02; (IPC1-7): H03M1/66; H03M3/02
Domestic Patent References:
| JP2210859A |
Foreign References:
| US4446438 |
Attorney, Agent or Firm:
Kazuo Shamoto
Shosuke Imai
Tadashi Masui
Yasushi Kobayashi
Shosuke Imai
Tadashi Masui
Yasushi Kobayashi