Title:
メモリハブアーキテクチャを有するメモリモジュールへのメモリアクセスを制御する方法およびシステム
Document Type and Number:
Japanese Patent JP4284621
Kind Code:
B2
Abstract:
A computer system includes a memory hub controller coupled to a plurality of memory modules. The memory hub controller includes a memory request queue that couples memory requests and corresponding request identifier to the memory modules. Each of the memory modules accesses memory devices based on the memory requests and generates response status signals from the request identifier when the corresponding memory request is serviced. These response status signals are coupled from the memory modules to the memory hub controller along with or separate from any read data. The memory hub controller uses the response status signal to control the coupling of memory requests to the memory modules and thereby control the number of outstanding memory requests in each of the memory modules.
Inventors:
Jedelo, Joseph M.
Lee, Terry Earl.
Lee, Terry Earl.
Application Number:
JP2004531860A
Publication Date:
June 24, 2009
Filing Date:
August 27, 2003
Export Citation:
Assignee:
APPLIED MATERIALS,INCORPORATED
International Classes:
G06F13/16; G06F12/00; G06F12/02; G06F12/06; G11C5/00; G06F
Domestic Patent References:
| JP9222956A | ||||
| JP2005529407A | ||||
| JP2005535038A | ||||
| JP2005535978A |
Foreign References:
| US20020038405 | ||||
| WO2002023353A1 |
Attorney, Agent or Firm:
Nomura Yasuhisa
Yoshiyuki Osuga
Yoshiyuki Osuga
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