Title:
マイクロコンピュータ
Document Type and Number:
Japanese Patent JP4882625
Kind Code:
B2
Abstract:
In a microcomputer provided with an instruction cache memory, in which a plurality of programs are executed, the execution time of each of the programs is ensured not be long. After dummy execution of high-priority processing in a time zone when a CPU of the microcomputer is in the process of executing idle processing, a high-priority processing program is stored in the instruction cache memory. The time for executing the high-priority processing afterwards with normal timing can be reduced because the high-priority processing program has already been stored in the instruction cache memory, whereby the hit rate is increased.
Inventors:
Hiroki Nakazato
Application Number:
JP2006250994A
Publication Date:
February 22, 2012
Filing Date:
September 15, 2006
Export Citation:
Assignee:
株式会社デンソー
International Classes:
G06F12/08; B60W10/04; B60W10/06; B60W10/10; B60W30/19; B60W50/00
Domestic Patent References:
| JP2005100034A | ||||
| JP2005215891A |
Other References:
光澤 敦,予測可能計算のためのページフレーム管理,コンピュータシステム・シンポジウム論文集,日本,社団法人情報処理学会,1999年11月29日,Vol.99 No.16,p.17~24
Attorney, Agent or Firm:
Tsutomu Adachi