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Title:
MICROPROCESSOR CONTROL SYSTEM
Document Type and Number:
Japanese Patent JPS58169226
Kind Code:
A
Abstract:

PURPOSE: To shorten the setting time of output data by detecting data width becoming longer than the width of a bus for the data and outputting the data through an address bus which has longer width than the bus width between data.

CONSTITUTION: In a microprocessor MPU10, when data to be outputted consists of >9 bits, outputs of incorporated accumulators are connected to address bus terminals A0, A1...A15. Then, address terminals A0...A12 among the address bus terminals are connected to data terminals D0...D7 of an output port 13-0. An address decoder 15 decodes an address output signal from the MPU10. On the basis of its decoding result, data transmitted from the address bus terminals A0-A7, and A8-A12 connected to plural output ports 13-0 and 13-1 are set in the output ports 13-0 and 13-1, thereby outputting them as output data.


Inventors:
WAKAMURA SHIYOUJI
Application Number:
JP5213382A
Publication Date:
October 05, 1983
Filing Date:
March 30, 1982
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G06F13/14; G06F13/16; G06F13/38; G06F13/40; (IPC1-7): G06F3/00
Attorney, Agent or Firm:
Akira Yamatani



 
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