PURPOSE: To attain high speed trap processing by providing a trap address register and saving a microprogram address for the processing executed next at generation of response waiting.

CONSTITUTION: When a response wait is generated, a microprogram issues a link return order to save a microprogram address for the processing executed next set to a CSAR13 to a CS address area of the entry of corresponding channel of a trap address register (TAR) 16 via a gate G4. When a response comes from an external device, a channel trap is generated and its channel number is set to a CHNR17. The TAR16 is searched according to the number, and when a bad bit of the entry coincident to the channel number is set, a CS address of the CS address area of the entry is read and set to the CSAR13 through a gate G6.