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Patent Searching and Data


Title:
MICROPROGRAM LOADING SYSTEM
Document Type and Number:
Japanese Patent JPH05165627
Kind Code:
A
Abstract:

PURPOSE: To dispense with the re-loading of a microprogram by a system reset operation and to accelerate system start-up processing.

CONSTITUTION: This system is equipped with a loader mechanism 2 which loads the microprogram on RAM(1)41-RAM(n)4n from an external memory device 10, an external switch 9 which supplies the suppression instruction signal of microprogram loading to those RAMs, a RAM write suppression circuit 3 which suppresses write on the RAM by the suppression instruction signal, a register circuit 6 which affects the suppression instruction signal on a register from the external switch 9, a stoppage instruction circuit 5 which stops the loader mechanism 2 by an affected suppression instruction signal, a power-on reset circuit 7 which detects a power source application state, and a power-on signal holding circuit 8 which holds a detected power application instruction signal and sends it out to the register circuit 6.


Inventors:
ISHIKAWA HIDENORI
Application Number:
JP32930391A
Publication Date:
July 02, 1993
Filing Date:
December 13, 1991
Export Citation:
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Assignee:
NEC IBARAKI LTD
International Classes:
G06F9/24; (IPC1-7): G06F9/24
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)