PURPOSE: To obtain a 1/n frequency divider having a large frequency division output level by setting a delay time of a closed loop to a nearly reciprocal of the frequency division output frequency and adding a frequency to be divided to the 2nd gate electrode of a dual gate FET.

CONSTITUTION: An even number (2m; m is a positive integer) of inverters 4 and a delay line 5 are connected in cascade between the drain electrode 6 and the 1st gate 3 of the dual gate FET 1. The delay time of the closed loop comprising the even number of inverters, the delay line 5 and the dual gate FET is set to a td being a nearly reciprocal of a frequency division output frequency fo/n, and since the dual gate FET acts like on stage of inverter for the frequency-divided output frequency, 2m+1 (odd number) stages are formed as the closed loop, and since a pseudo ring oscillator is constituted, the oscillation is oscillated easily at a frequency of 1/td.