Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
MISRECOGNITION PREVENTING DEVICE FOR DATA OF SEMICONDUCTOR STORAGE DEVICE
Document Type and Number:
Japanese Patent JPH11120086
Kind Code:
A
Abstract:

To prevent RAM data from being misrecognized with simple constitution by arranging RAMs, and storing the same data on the different RAMs and making different the bit positions of the same data in respective address areas.

One piece of data '0' here has the bit position of an address 002D of a RAM 11 set to a 1st position (right end). In a RAM 12, this '0' has the bit position of an address 0089 of the RAM 12 set to a 4th position (from the right end). In a RAM 13, this '0' has the bit position of an address 00C5 of the RAM 13 set to a 6th position (from the right end). Thus, when one set of data is stored in more than one address area, RAMs 11 to 14 are arranged, and the same data are stored in the different RAMs and the bit positions of the same data in address areas are made different.


Inventors:
TOMITA HIROFUMI
Application Number:
JP27615397A
Publication Date:
April 30, 1999
Filing Date:
October 08, 1997
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
AISIN AW CO
International Classes:
G06F12/16; G11C29/00; G11C29/04; (IPC1-7): G06F12/16; G11C29/00
Attorney, Agent or Firm:
Mamoru Shimizu (1 person outside)