PURPOSE: To remarkably improve the processing speed by providing a data conversion circuit, a marging bit addition circuit, a rule violation detection circuit, a marging bit selection circuit and a digital sum value calculation circuit.

CONSTITUTION: The data of h-bit inputted from a line 11 is converted into a d-bit by a data conversion circuit 1 and its output 12 is added by a k-bit merging bit by a merging bit addition circuit 2, and the result is outputted from a line 21. In converting a data by a circuit 1, the number of Os at the head and the end of the data is outputted as a signal 13 at the same time, signals 13, 12 and 41 are inputted to a rule violation detection circuit 3 to output the presence violation as to each selected merging bit from a line 31. A merging bit selection circuit 4 receives a digital sum value 51, a polarity 52, a digital sum value 14 after the merging bit and the rule violation signal 31 at the point of time inserting the merging bit outputted from the digital sum value calculation circuit 5 and outputs a marging bit minimizing the digital sum value and not being the rule violation from a line 41.