PURPOSE: To reduce the locking time at power at power application by providing two sets of PLL loops consisting each of a reference oscillator and a voltage controlled oscillator, comparing the phase at a high frequency at power application and comparing the phase at a low frequency when the lock is finished.

CONSTITUTION: A reference crystal oscillator 14 and a voltage controlled oscillator VCO11 are provided with two PLL loops of a 1/M1 frequency divider 21, a 1/N1 frequency divider 23, a phase comparator PD125 and a 1/M2 frequency divider 24, a 1/N2 frequency divider 25 and a phase comparator PD226. At application of power, a changeover switch 27 is thrown to the position of the PD125 by a switching signal 28, the phase is compared with a frequency high in the frequency dividing ratio of 1/M1, 1/N1, the compared output is added to a modulating input 19 at an adder 17 via an LPF16, the resultant signal controls the VCO11 to take the phase synchronism. When the locking of synchronism is finished, the switch 27 is thrown to the position of the PD2 26, the phase is compared in a frequency lower in the frequency dividing ratio of 1/(M1× M2), 1/(N2×M2) and a modulation output signal is outputted from a terminal 18. After the phase synchronism is taken at a high frequency and fast locking is executed, the phase synchronism is taken at a low frequency to decrease the modulation distortion.