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Patent Searching and Data


Title:
MODULE FORMED INTO CHIP
Document Type and Number:
Japanese Patent JPH0195602
Kind Code:
A
Abstract:

PURPOSE: To eliminate the deterioration in the characteristic and to attain the miniaturization by forming an input/output strip line on a dielectric board, packing a chip parts such as an FET chip to a ground conductor and connecting it to the input/output strip line by strip line/slot line conversion.

CONSTITUTION: A GaAs FET chip 1, power supply bypass capacitors 4, 5, and chip parts such as thin film resistors 6, 7 requiring hermetic seal are packed on the ground conductor face of the dielectric board 19. The input/output of the chip parts is coupled in terms of magnetic field with a slot line 20 on the dielectric board 19 and power is supplied from power voltage supply connector pins 10, 11 to a gate and a drain of the GaAs FET chip 1. The input/output strip lines 12, 13 vapor-deposited onto the dielectric board 19 are connected to a slot line 20 on the rear face by the strip/slot line conversion. The shield case 14 for hermetic seal made of a ceramic or a metallic material is connected to the dielectric board 19 and sealed by using a cover 19. Thus, the deterioration in the high frequency characteristic is prevented and the size is reduced.


Inventors:
IZUMI ISAO
Application Number:
JP25587687A
Publication Date:
April 13, 1989
Filing Date:
October 08, 1987
Export Citation:
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Assignee:
NEC CORP
International Classes:
H01L23/02; H01L21/338; H01L23/04; H01L23/12; H01L29/80; H01L29/812; H01P3/08; H01P5/02; H01P5/08; H01P5/10; H03F3/60; (IPC1-7): H01L23/02; H01L23/04; H01L23/12; H01L29/80; H01P3/08; H01P5/08; H03F3/60
Domestic Patent References:
JPS55128901A1980-10-06
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)