To schedule a module type chip selection control circuit by providing an address decoding stage having a first number of address decoders, a control stage having a second number of control units, and pin configuration stage having a third number of pin configuration logic circuits.
The number of memory areas, the depth of an access pipeline, and the number of chip selecting signals are independent from each other and can be changed in accordance with the design of a chip. A control stage contains an early-stage pipeline control circuit 186 which pipelines a run-on memory cycle based on the characteristics of an area from which control units 170 and 180 are accessed. The circuit 186 provides a series of efficient pipelined memory access cycles by executing one set of pipelining rules for guaranteeing the complete and appropriate termination of a data cycle together with the units 170 and 180.
JIEIMUZU BII EIFUAATO
BAJIRU JIEI JIYAKUSON
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