Title:
MONOLITHIC ELECTRONIC DEVICE
Document Type and Number:
Japanese Patent JPH01166156
Kind Code:
A
Abstract:
PURPOSE: To reduce a space occupied by a decoder by providing one decoder common to a memory plane composed of a ROM and a memory plane composed of a programmable memory. CONSTITUTION: This integrated circuit is provided with a processor 1 for data processing, a memory 2 for processing, and a memory plane 3. The memory plane 3 is a mixed memory plane and is provided with a memory plane 4 having a ROM cell. The memory plane 3 is provided also with a memory plane 5 having a programmable memory cell. The memory 2 for processing is connected to the processor 1 for data processing through a bus 6, a decoder 7 for bit line, and a decoder 8 for word line. The memory plane 3 is connected to the processor 1 for data processing through the same bus 6 and the single decoder common to two memory planes 4 and 5. This single decoder is provided with a decoder 9 for bit line and a decoder 10 for word line, and a preliminarily programmed simple instruction 11 is stored in the monolithic integrated circuit.
Inventors:
ROORAN SURUJIYAN
JIRU RIJIMATSUKU
JIRU RIJIMATSUKU
Application Number:
JP29448188A
Publication Date:
June 30, 1989
Filing Date:
November 21, 1988
Export Citation:
Assignee:
SGS THOMSON MICROELECTRONICS
International Classes:
G06F12/06; G06F15/78; G11C11/00; G11C16/04; G11C17/00; (IPC1-7): G06F12/06; G06F15/06; G11C17/00
Domestic Patent References:
| JPS62224853A | 1987-10-02 | |||
| JPS5921058A | 1984-02-02 | |||
| JPS5148951A | 1976-04-27 | |||
| JPS56165984A | 1981-12-19 | |||
| JPS54121628A | 1979-09-20 |
Attorney, Agent or Firm:
Takashi Koshiba