Title:
MOS FOUR-QUADRANT MULTIPLIER
Document Type and Number:
Japanese Patent JP2540783
Kind Code:
B2
Abstract:
PURPOSE: To realize a MOS four-quadrant multiplier which is formed in a semiconductor integrated circuit with a linear input voltage range.
CONSTITUTION: The positive phase of a second input signal V2 is inputted to one of two-quadrant multipliers with the first input signal V1 as a common input and an opposite phase V2' is inputted to the other two-quadrant multiplier. The four two-quadrant multipliers are constituted as shown in the figure and a result with good linearity is outputted in accordance with the polarity of the two signal inputs.
Inventors:
KIMURA KATSUHARU
Application Number:
JP13046994A
Publication Date:
October 09, 1996
Filing Date:
June 13, 1994
Export Citation:
Assignee:
NIPPON ELECTRIC CO
International Classes:
G06G7/163; (IPC1-7): G06G7/163
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)