To provide an MOS multiplication circuit which can be formed on a semiconductor integrated circuit.

The sources of first to fourth transistors, for which a constant voltage is impressed between a gate and a source, are connected in common, first to fourth differential transistors composed of transistors M5-M12, the sources of which are connected in common and the drains of which are also connected in common, are connected to the drains of transistors M1-M4 while being driven by a ground or constant current source and when first and second input voltages are defined as V1 and V2, V3 is defined as an arbitrary voltage and (a), (b) and (c) are defined as arbitrary constants, voltages aV1+V3, bV2+V3, (a-c)V1+V3, (b-1/c)V2+V3, (a-c)V1+V3, bV2+V3, aV1+V3 and (b-1/c)V2+V3 are respectively impressed to the gates of the transistors M5-M12. Then, a differential current between the sum current of output currents from the first and second differential transistors and the sum current of output currents from the third and fourth transistors is defined as an output current and a current proportional to the product of first and second input voltages is outputted.