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Patent Searching and Data


Title:
MOS MULTIPLIER CIRCUIT AND FREQUENCY MIXER CIRCUIT
Document Type and Number:
Japanese Patent JP2000048111
Kind Code:
A
Abstract:

To obtain a practical MOS multiplier circuit which is said to be suitable when it is formed on a semiconductor integrated circuit by outputting a current component proportional to the product of voltage varied with respect to a bias voltage so as to suppress the increase of the circuit scale.

In stead of first and second input currents, first and second input voltages VX, VY are respectively connected to between first bias voltages VB and the connecting points of the gate and drain of transistors M1 and M6. In addition, at the time of setting the first input voltage VX to be a high frequency (RF) signal and the second input voltage VY to be a local (LO) signal, frequencies of the difference and the sum of an RF frequency and an LO frequency are obtained from the product of an RF signal voltage and an LO signal voltage and this circuit can be used as a frequency mixer circuit. Since, the circuit is realized with two input terminals, the practical MOS multiplier circuit which is suitable for an integrated circuit by reducing the increase of the circuit scale can be realized.


Inventors:
KIMURA KATSUHARU
Application Number:
JP21732398A
Publication Date:
February 18, 2000
Filing Date:
July 31, 1998
Export Citation:
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Assignee:
NEC CORP
International Classes:
G06G7/163; H03D7/12; H03D7/14; (IPC1-7): G06G7/163; H03D7/12; H03D7/14
Attorney, Agent or Firm:
Asato Kato