Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
MOS MULTIPLIER CIRCUIT
Document Type and Number:
Japanese Patent JP2000076371
Kind Code:
A
Abstract:

To provide a MOS multiplier circuit of a comparatively small circuit scale by providing a multiplier core circuit commonly connecting the drains of respective first/second transistors so as to constitute one output terminal and commonly connecting the drains of respective third/fourth transistors so as to constitute the other output terminal.

The circuit is provided with MOS transistors M1 and M2 forming a first multiplier circuit, where sources are grounded and V1+v1, V2+v2 are applied to gates and drains commonly connected and connected with a power source through a resistor R. Similarly the circuit is provided with MOS transistors M3, M4 forming a second multiplier circuit applied with V1-v1, V2-v2, MOS transistors M5, M6 forming a third multiplier circuit applied with V1+v1, V2-v2 and MOS transistors M7, M8 forming a fourth multiplier circuit applied with V1-v1, V2+v2. A dynamic range in outputting is secured by providing a multiplier core circuit constituted like this.


Inventors:
KIMURA KATSUHARU
Application Number:
JP24274298A
Publication Date:
March 14, 2000
Filing Date:
August 28, 1998
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
NEC CORP
International Classes:
G06G7/163; H03D7/12; H03D7/14; (IPC1-7): G06G7/163; H03D7/12; H03D7/14
Attorney, Agent or Firm:
Asato Kato