To terminate an arithmetic operation of one accumulated value (AE) at an earlier stage than that of a conventional arithmetic operation by reducing a pixel number for the arithmetic operation for matching, operating arithmetic operation for a plurality of pixel strings in parallel and controlling read sequence of a reference pixel.

The proposed circuit is provided with a shift register 103 that stores reference pixels and controls read sequence of the reference pixels to conduct the arithmetic operation with respect to a plurality of pixels in parallel thereby terminating the AE arithmetic operation in an earlier stage than that of conventional arithmetic operations. The arithmetic operation for each field is attained by connecting odd order and even order numbers of N-pieces of shift registers 103 separately in a cyclic fashion to provide pixels of an object block sequentially to (N-pieces for one column) arithmetic units 104, 105, and registers and adders 106, 107 to latch the result are provided to obtain the result for each frame.