To provide a circuit configuration wherein a wiring pattern is designed with ease, without regarding concentration of energy to one MOS transistor in a large current circuit.

When an off signal is inputted to the gates of MOS transistors T1, T2, and Tn of a chopper circuit 14 from a control circuit 13, the MOS transistor T1, T2, and Tn are all turned off. At that time, a surge voltage is applied to a Zener diode 16 to turn on an MOS transistor T0, which remains in on state until the surge voltage is absorbed. With a clamping circuit 15 provided separately, no surge voltage is applied to the chopper circuit 14. Thus, no energy is concentrated, for destruction, on any one of MOS transistors T1, T2, and Tn due to dispersion in inductances 11, 12, and 1n of wiring of the chopper circuit 13, resulting in easier wiring pattern design.