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Title:
MOUNTING AND SEALING STRUCTURE FOR SEMICONDUCTOR COMPONENT AND METHOD FOR MOUNTING AND SEALING THE SAME
Document Type and Number:
Japanese Patent JP2003007739
Kind Code:
A
Abstract:

To reduce air enclosed in a gap between a circuit board and a semiconductor component by a cover when the component is solder mounted on a surface of the board and the component is sealed with the cover made of a synthetic resin.

A method for mounting and sealing the semiconductor component comprises a step of filling a sheet-like filler 7 made of a heat resistant insulator in the gap between a bottom of a package 3 of the component 1 and the surface of the circuit board 4 for mounting the package. Since the board 4 is previously coated with a solder paste, when the board 4 after the package 3 is mounted is introduced into a heating furnace, the board 4 is soldered to the package 3. The method further comprises the steps of coating a liquid heat resistant synthetic resin on the entire package 3 and the board after soldering, and curing the resin.


Inventors:
MIZUHARA SEITAROU
Application Number:
JP2001184842A
Publication Date:
January 10, 2003
Filing Date:
June 19, 2001
Export Citation:
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Assignee:
ROHM CO LTD
International Classes:
H05K3/28; H01L21/56; (IPC1-7): H01L21/56; H05K3/28
Domestic Patent References:
JPS61183575U1986-11-15
JPH0462888A1992-02-27
JPS62206895A1987-09-11
Attorney, Agent or Firm:
Akio Ishii (2 outside)