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Patent Searching and Data


Title:
MOUNTING SYSTEM OF ELECTRONIC CIRCUIT
Document Type and Number:
Japanese Patent JPS5596712
Kind Code:
A
Abstract:

PURPOSE: To make impedance uniform to reduce distortion of the waveform by fitting a capacitor to the wiring part, where no load is fitted, in the system where the delay time for propagation through wiring is longer in comparison with the rise and break time of signals.

CONSTITUTION: Interval l of loads IC 1a∼1f is shorter than distance t0/td where a signal is propagated through the signal line of propagation delay time td per unit length within rise and break time t0 of the signal. Interval l0 between driving IC 3 and load ICs is sufficiently longer than t0/td. In this circuit, the swaveform is distorted due to negative reflection of characteristic impedance Z3 of the signal line across capacities 6a∼6f> characteristic impedance Z2 of the signal line across IC 1a∼1i. Therefore, capacities 6a∼6f are fitted at interval l1(l1<t0/td) to make characteristic impedance Z3 equal to Z2. Thus, a high-speed transmission circuit without delay loss can be realized.


Inventors:
ISHIHARA KAZUNORI
Application Number:
JP433379A
Publication Date:
July 23, 1980
Filing Date:
January 18, 1979
Export Citation:
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Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
G11C11/41; H01P9/00; H03H7/38; H04B3/00; H04B3/04; H04B3/26; H04L25/02; (IPC1-7): G11C11/34; H03H7/38; H04B3/20; H04B3/26; H04L25/02