Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
MULTI-CHIP LSI PACKAGE
Document Type and Number:
Japanese Patent JPS5843553
Kind Code:
A
Abstract:

PURPOSE: To enable the low impedance of power source wirings and the high speed operation through reduction of noise due to power supply by utilizing the multi wiring layer provided in the internal layer of a laminated ceramic substrate as the power source conductor wiring.

CONSTITUTION: The through hole pads 7 connected to through holes 12 and terminating resistors 8 are formed on the surface of substrate 9 and input/output terminals 11 are provided at rear side. The terminals 11 are bazed so that they are connected to the through holes 12. A multi wiring layer 5 is formed covering the terminating resistors 8 and through hole pads 7 and accommodates multi wirings 6. Terminals of an LSI chip 1 are connected by bonding within a chip carrier 2 which is connected to a connecting pad 4, thereby connection to the multi wirings 6 within the multi wiring layer 5 can be established.


Inventors:
WATARI TOSHIHIKO
Application Number:
JP14193481A
Publication Date:
March 14, 1983
Filing Date:
September 08, 1981
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
NIPPON ELECTRIC CO
International Classes:
H05K3/46; H01L23/538; H01L23/64; (IPC1-7): H01L23/52; H05K1/11
Attorney, Agent or Firm:
Toshi Inoguchi



 
Previous Patent: 情報フロー制御プログラム

Next Patent: JPS5843554