Title:
直列入/出力インターフェスを有するマルチポートメモリ素子
Document Type and Number:
Japanese Patent JP4948952
Kind Code:
B2
Abstract:
A semiconductor memory device includes: a plurality of ports configured to perform a serial input/output (I/O) data communication with external devices; a plurality of banks configured to perform a parallel I/O data communication with the ports; a global data bus configured to transmit a signal between the banks and the ports; a test mode determiner configured to determine an operation mode of the semiconductor memory device by generating a test mode enable signal in response to a test mode control signal; a test I/O controller configured to transmit and receive a test signal with the ports in response to the test mode enable signal during a port test mode; and a plurality of selectors, each of which is configured to receive the test signal output from the corresponding port in series and feedback the test signal to the corresponding port.
Inventors:
Masaho
Lee
Lee
Application Number:
JP2006259624A
Publication Date:
June 06, 2012
Filing Date:
September 25, 2006
Export Citation:
Assignee:
Hynix Semiconductor Inc.
International Classes:
G11C29/12; G01R31/28; G11C11/401
Domestic Patent References:
| JP60106247A | ||||
| JP2003304208A | ||||
| JP2005322375A | ||||
| JP63280544A | ||||
| JP63206052A | ||||
| JP10093582A | ||||
| JP63036457A | ||||
| JP8062298A | ||||
| JP9204372A | ||||
| JP200485526A |
Attorney, Agent or Firm:
Ichiro Kudo