Title:
マルチポートメモリおよび半導体装置
Document Type and Number:
Japanese Patent JP6637872
Kind Code:
B2
Abstract:
A memory circuit includes: a control circuit generating first and second start signals within a single signal cycle of an input clock signal; an address control circuit coupled to a plurality of address ports for receiving a plurality of address signals and activating one of word lines corresponding to one of the address signals based on the first or second start signals; and a data input/output circuit for writing or reading data by selecting one of memory cells coupled to the activated word line. The control circuit includes: a start signal generation unit that generates the first start signal in response to a first pulse signal and the second start signal in response to a second pulse signal, and a pulse signal generation unit that generates the first pulse signal in response to the input clock signal and the second signal in response to the first start signal.
Inventors:
Yuichiro Ishii
Application Number:
JP2016211731A
Publication Date:
January 29, 2020
Filing Date:
October 28, 2016
Export Citation:
Assignee:
Renesas Electronics Corporation
International Classes:
G11C11/413; G11C7/10; G11C7/22; G11C8/16
Domestic Patent References:
| JP2000173270A | ||||
| JP2013157051A | ||||
| JP2010135025A |
Attorney, Agent or Firm:
Fukami patent office
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