PURPOSE: To carry out subtraction at a high speed without increasing the circuit scale and to make a bit signal many-valued and use the multi-valued signal in common by providing a logic circuit means and a multi-value circuit means and performing the subtraction on the basis of the output of the multi-value circuit means.

CONSTITUTION: A ternary subtracter consists of input/output elements 10-19, AND circuit elements (AND element) 20-35 as the logic circuit means, and multi-value function elements 36-75 as the multi-value circuit means, input/output elements 76 and 77, AND elements 78-83, OR circuit elements (OR element) 84-88, and input/output elements 89 and 90, and a one-bit delay circuit 91. Then the AND circuit elements 20-35 input plural signals and output specific logical results, and the multi-value function elements 36-75 are connected to the AND circuit elements 20-35 and output specific many-valued signal on the basis of the logical results, so that the subtraction is carried out on the basis of the outputs of the many-valued function elements 36-75.