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Title:
MULTICHIP PACKAGE
Document Type and Number:
Japanese Patent JP2010107388
Kind Code:
A
Abstract:

To provide a multichip package capable of performing inspection simultaneously even when each supply voltage has each different potential between circuit chips.

This multichip package 100 includes a plurality of circuit chips connected electrically to the inside of the package, and has an inspection mode for inspecting the circuit chips. The plurality of circuit chips include a driver chip 20, and an LSI chip 10 wherein a protection diode 11 is connected to a terminal, and a supply voltage during an inspection mode time has a lower potential than a supply voltage of the driver chip 20, and also include the first level shift circuit 33a for performing level shift of a signal from the driver chip 20 so as to have the same potential as the supply voltage of the LSI chip 10 during the inspection mode time and outputting it to the LSI chip 10.


Inventors:
NASU TADASHI
MAEDA KOICHI
Application Number:
JP2008280398A
Publication Date:
May 13, 2010
Filing Date:
October 30, 2008
Export Citation:
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Assignee:
DENSO CORP
International Classes:
G01R31/28; H01L21/822; H01L25/04; H01L25/18; H01L27/04
Attorney, Agent or Firm:
Kazuyuki Yahagi
Taihei Nonobe



 
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