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Patent Searching and Data


Title:
MULTILAYER INTERCONNECTION SUBSTRATE
Document Type and Number:
Japanese Patent JPS63281499
Kind Code:
A
Abstract:

PURPOSE: To prevent the generation of porous state by the effect of the fluidity of amorphous glass, reduce the rate of moisture absorption, and obtain a high insulating property, by stacking the following in order on a plurality of conductor layers formed on an insulating substrate; a first insulating layer of crystallized glass, a second insulating layer of amorphous glass, and a third insulating layer the same as the first layer.

CONSTITUTION: On an insulating substrate 1, wiring conductor layer 21∼28 are formed by printing and calcining silver palladium system conductor paste. Between arbitrary wiring conductor layers 24∼28 required for connection, a first insulating layer 3 is formed, by printing and calcining paste of SiO2 system crystallized glass. Thereon a second insulating layer 4a is formed, by printing and drying paste type amorphous glass of SiO2 system. Thereon a third insulating layer 5 of the same quality crystallized glass as the insulating layer 3 is formed. On the insulating layer 5, a wiring conductor layer 6 is formed across the wiring layers 24∼28, and resistors 7, 8 are formed at an arbitrary position so as to bridge the conductor layers 21, 22 and 26, 27, by printing and calcining terbium oxide system paste. An overcoat layer 9 is formed, by printing and calcining amorphous glass, etc., on the above-mentioned insulating layer except the end-portions of the conductor layers 21∼28.


Inventors:
YAMADA TAKEJI
Application Number:
JP11655187A
Publication Date:
November 17, 1988
Filing Date:
May 13, 1987
Export Citation:
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Assignee:
SHARP KK
International Classes:
H05K3/46; (IPC1-7): H05K3/46
Attorney, Agent or Firm:
Suzuki Harumi