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Title:
MULTILAYER SUBSTRATE, METHOD AND DEVICE FOR DESIGNING MULTILAYER SUBSTRATE, PROGRAM AND COMPUTER READABLE MEMORY MEDIUM
Document Type and Number:
Japanese Patent JP2002299842
Kind Code:
A
Abstract:

To provide a tamper-proof multilayer substrate without increasing a manufacturing cost.

A signal line, which requires tamper-proof property, is a signal line connecting a terminal 102 and a terminal 115, and the signal line is wired by means of a foil 103, a via 104, a foil 111, a via 105, a foil 112, a via 106 and a foil 113. Any part existing in a surface layer of a wiring of a signal line requiring tamper-proof property is disposed below a component. That is, a component 101 comprises the foil 103 and a tip part of the via 104 in its occupation region. A component 107 comprises the top part of the via 105 in its occupation region. The component 108 comprises the top part of the via 106 in its occupation region. The component 109 comprises the top part of the via 104 in its occupation region. The component 110 comprises the top part of the via 105 in its occupation region. The component 114 comprises the foil 113 and the top part of the via 106 in its occupation region.


Inventors:
TAKAHASHI EIJI
FUKUMOTO YUKIHIRO
SAITO YOSHIYUKI
SHIBATA OSAMU
TANIMOTO SHINICHI
NAKAYAMA TAKESHI
Application Number:
JP2001395053A
Publication Date:
October 11, 2002
Filing Date:
December 26, 2001
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
G06F17/50; H01P1/00; H05K3/00; H05K3/46; (IPC1-7): H05K3/46; H01P1/00; H05K3/00
Attorney, Agent or Firm:
Nakajima Shiro



 
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