Title:
MULTILAYERED WIRING METHOD OF INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPH0786407
Kind Code:
A
Abstract:
PURPOSE: To increase wiring efficiency of the layout of an integrated circuit, and provide a multilayered wiring method of an integrated circuit wherein wiring distance is short, by effectively using each wiring layer, in an integrated circuit wherein multilayered wiring is performed.
CONSTITUTION: In the multilayered wiring method of an integrated circuit wherein (m) kinds of wiring layers L1, L2 and L3 ((m) is three or larger positive integer) are formed, the main wiring directions of the (m) kinds of wiring layers L1, L2 and L are made different (n) kinds of wiring directions R1, R2 and R ((n) is positive integer satisfying 3≤≤m).
Inventors:
MIURA SHINPEI
Application Number:
JP22477393A
Publication Date:
March 31, 1995
Filing Date:
September 09, 1993
Export Citation:
Assignee:
FUJITSU LTD
International Classes:
H01L21/82; H01L21/3205; H01L21/822; H01L23/52; H01L27/04; (IPC1-7): H01L21/82; H01L21/3205; H01L21/822; H01L27/04
Attorney, Agent or Firm:
Yasuo Ishikawa
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