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Patent Searching and Data


Title:
MULTIPLE TRANSMISSION SYSTEM
Document Type and Number:
Japanese Patent JP01117535
Kind Code:
A
Abstract:

PURPOSE: To reduce the circuit scale in comparison with the transmission system employing a conventional multi-frame synchronizing circuit by applying pulse frequency modulation based on a transmission frame signal according to a sub signal at the sender side and multiplexing the signal to a specific idle bit of a transmission data signal and sending the result.

CONSTITUTION: A pulse frequency modulation circuit 103 at the sender side generates a signal 155 subject to pulse frequency modulation in response to the sub data signal 154 based on the frame signal added by a frame addition circuit 101. A multiplexer circuit 102 multilexes the signal 155 onto a specific bit of the main data signal. The frame addition circuit 101 receives a transmission frame signal 151 and a transmission clock signal 152, adds a frame signal to the data signal generated by the multiplexer circuit 102 and sends the result. On the other hand, a frame synchronizing circuit 104 at the receiver side takes frame synchronization, a demultiplexer circuit 105 segments one bit multiplexed at the output and recovers the pulse frequency modulation output and a pulse frequency demodulation circuit 106 demodulates it into a pulse frequency to obtain a sub signal 160 demultiplexed according to the pulse frequency.


Inventors:
Namikado, Nagahiko
Application Number:
JP1987000275266
Publication Date:
May 10, 1989
Filing Date:
October 30, 1987
Export Citation:
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Assignee:
NEC CORP
International Classes:
H04J3/00; H04J3/00; (IPC1-7): H04J3/00