To provide the power saving circuit of small scale for digital signal processing by composing capacitive coupling of plural capacitances of capacity proportional to the sum of weight of bit pairs corresponding to respective AND circuits, connecting the output of this capacitive coupling to an amplifier circuit and outputting the multiplied result as an analog voltage.
Concerning the combination of all the digital data of 3 bits of a0-a2 and the digital data of 3 bits of b0-b2, the AND is respectively obtained by AND circuits G91-G99. The respective outputs of these AND circuits G91-G99 are respectively inputted to MUX91, SEL91, MUX92, SEL93 and MUX93 and these outputs are respectively connected to capacitances C91-C96 so that capacitive coupling is constituted. The output of this capacitive coupling is inputted to the inverted input of an operational amplifier AMP9, the capacity in proportion to the sum of weight of these respective AND inputs is calculated and the multiplied result is outputted as an analog voltage.
Next Patent: CLEANING DEVICE FOR INFORMATION RECORDING MEDIUM