Title:
MULTIPLICATION CIRCUIT
Document Type and Number:
Japanese Patent JP2933256
Kind Code:
B2
Abstract:
PURPOSE: To make highly accurate and diversified arithmetic possible with a small-scale circuit by outputting the multiplied result by operating calculation with voltage difference among respective capacitances.
CONSTITUTION: This multiplication circuit is provided with capacitances C0-C3 with different capacity connected to an output terminal, an nMOS is connected at the source to one terminal of respective capacitances C0-C3, a pMOS is connected at the drain, the drain of the pMOS is grounded, and the source of the nMOS is connected to a common input voltage Vi. When the gate voltages of toggle switches SW0-SW3 corresponding to the C0-C3 are defined as a0-a3, only the switch of the gate voltage at a high level guides only the input voltage Vi to the capacitance. When voltages to be impressed to the respective capacitances C0-C3 are defined as V0-V3, a voltage V0 is generated at out. Therefore, unit capacity (c) is decided and C0-1c, C1-2c, C2=4c and C3-c8 are set so that any arbitrary integer arithmetic can be performed by opening/closing the SW0-SW3.
Inventors:
KOTOBUKI KOKURYO
YO KOREYASU
UIWATSUTO UONWARAUIPATSUTO
TAKATORI SUNAO
YAMAMOTO MAKOTO
YO KOREYASU
UIWATSUTO UONWARAUIPATSUTO
TAKATORI SUNAO
YAMAMOTO MAKOTO
Application Number:
JP29213492A
Publication Date:
August 09, 1999
Filing Date:
October 06, 1992
Export Citation:
Assignee:
TAKATORI IKUEIKAI KK
SHAAPU KK
SHAAPU KK
International Classes:
G06G7/163; (IPC1-7): G06G7/163
Domestic Patent References:
| JP6154717A |
Other References:
【文献】トランジスタ技術 Special No.16,CQ出版社,1989年7月1日発行,第22頁-第23頁
Attorney, Agent or Firm:
Yamamoto Makoto