Title:
MULTIPLICATION CIRCUIT
Document Type and Number:
Japanese Patent JP3117048
Kind Code:
B2
Abstract:
PURPOSE: To provide the multiplication circuit which suppresses the number of steps longitudinally piling transistors at a minimum and is convenient for voltage reduction.
CONSTITUTION: While using 1st-4th basic circuits U1-U4, terminals A of the 1st and 3rd basic circuits U1 and U3 are connected to a 1st terminal 1, the terminals A of the 2nd and 4th basic circuits U2 and U4 are connected to a 2nd terminal 2, terminals b of the 1st and 4th basic circuits U1 and U4 are connected to a 3rd terminal 3, and the terminals B of the 2nd and 3rd basic circuits U2 and U3 are connected to a 4th terminal 4 respectively. Then, terminals C of the 1st and 2nd basic circuits U1 and U2 are connected in common, and the terminals C of the 3rd and 4th basic circuits U3 and U4 are connected in common.
Inventors:
Onodera Kiyomitsu
Application Number:
JP8106393A
Publication Date:
December 11, 2000
Filing Date:
March 17, 1993
Export Citation:
Assignee:
Nippon Telegraph and Telephone Corporation
International Classes:
G06G7/163; (IPC1-7): G06G7/163
Domestic Patent References:
| JP54152444A | ||||
| JP59184970A | ||||
| JP60146371A | ||||
| JP61174821A | ||||
| JP5225365A | ||||
| JP757026A |
Attorney, Agent or Firm:
Masataka Kobayashi