Title:
MULTIPLIER CIRCUIT
Document Type and Number:
Japanese Patent JP3152715
Kind Code:
B2
Abstract:
PURPOSE: To reduce a bypass between input terminals by inserting a base ground transistor(TR) between amplifier sections of 1st and 2nd input signals to prevent the deterioration in the common mode rejection ratio at a high frequency side due to a parasitic capacitance of the TR.
CONSTITUTION: First and 2nd common base TRs 13, 14 are inserted between a common emitter terminal of 1st and 2nd differential amplifier circuits TRs 1, 2 and TRs 3, 4 and the output terminal pair of plural 3rd differential amplifier circuit TRs 5-8. The emitter area of the TRs 13, 14 is set smaller than the maximum emitter area of the TR used for the TRs 5-8. Thus, the impedance when viewing the output terminal pair of the TRs 5-8 from the common emitter terminal of the TRs 1, 2 and the TRs 3, 4 is set larger than that without the TRs 13, 14. Thus, the part of the TRs 5-8 receives a DC offset, then even when the emitter area is increased, the reduction in the common mode rejection ratio of the TRs 1, 2 and the TRs 3, 4 due to a large parasitic capacitance of the TRs is prevented, and a bypass signal from terminal pairs L01, L02 to the input terminals M01, M02 is reduced.
Inventors:
Takafumi Yamaji
Oath Takahashi
Hiroshi Tanimoto
Oath Takahashi
Hiroshi Tanimoto
Application Number:
JP2807792A
Publication Date:
April 03, 2001
Filing Date:
February 14, 1992
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
H03D1/22; G06G7/163; H03D7/14; H03F3/45; (IPC1-7): H03D7/14; H03D1/22; H03F3/45
Attorney, Agent or Firm:
Takehiko Suzue